A common problem found in high performance microprocessor designs is detecting and handling load address dependencies, and in particular, load and store memory address conflicts. Generally, a load and store memory address conflict occurs when a load instruction follows a store instruction directed to the same memory address, and the store instruction has not yet been committed to memory or otherwise cleared. A load and store memory address conflict is typically referred to as a “load-hit-store” condition. Another load address dependency is a load and reload memory address conflict. Generally, a load and reload memory address conflict occurs when a load instruction follows an earlier load, or reload, instruction directed to the same memory address, and the earlier load instruction has not yet been executed or otherwise cleared. A load and reload memory address conflict is typically referred to as a “load-hit-reload” condition. It will be understood to one skilled in the art that, generally, a load-hit-reload condition can be an address collision with an older load-type operation that has not yet executed, and that a load-type operation can include any operation that is operable to read data into the processor, whether to be employed by software or stored in a cache.
Several approaches have been undertaken to address load address dependencies, and in particular load-hit-store conditions. In typical low frequency designs, one approach is to employ a handshake mechanism between a Load/Store Unit (LSU) and the issue logic that allowed the LSU to stall in response to a load-hit-store condition. However, the LSU handshake mechanism is not effective in higher frequency designs.
One approach to handle load-hit-store conditions in a high frequency design is to employ an issue queue in the issue logic to issued load/store instructions that have been sent to the LSU. When the LSU detects a load-hit-store condition, the offending instruction is rejected back to the issue logic, typically through a reject signal sent from the LSU to the issue queue. The issue queue then re-issues the offending instruction in a later load/store pipeline slot. However, this approach typically requires a complex issue queue mechanism, which incurs relatively high hardware size and power costs.
Therefore, there is a need for a system and/or method for a load address dependency mechanism in a high frequency, low power processor system that addresses at least some of the problems and disadvantages associated with conventional systems and methods.